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LF3370
DEVICES INCORPORATED
High-Definition Video Format Converter
LF3370
DEVICES INCORPORATED
High-Definition Video Format Converter
DESCRIPTION
The LF3370 is a video format converter capable of operating at HDTV data rates. This device converts to and from any of the various SDTV/HDTV digital video formats by utilizing an internal 3 x 3 Matrix Multiplier and two 1:2 Interpolation/2:1 Decimation Half-Band Filters. Using the Input Demultiplexer and Output Multiplexer, the LF3370 can accept and output interleaved or non-interleaved video. For example, R/G/B/Key data can be color space converted to Y/U/V/Key and down-converted to 4:2:2:4. By re-arranging the order of the functional sections, the opposite conversion can be achieved. The coefficients for the 3 x 3 Matrix Multiplier are fully user programmable to support a wide range of color space conversions. The two Interpolation/Decimation Half-Band Filters are fully compliant with SMPTE 260M. Input and Output Bias Adders are included for removing or adding a user-defined bias into the video signal. In addition, three programmable 1K x 13-bit Look-Up Tables (LUTs) have also been included for various uses such as gamma correction. A Scaler has been included on the Key Channel for scaling to a desired magnitude using user programmable coefficients. Input signals can also be forced to user-defined levels for horizontal blanking. Furthermore, Round/ Select/Limit (RSL) circuitry is provided at the end of various stages to provide the best possible conversions without color violations. For additional flexibility, the Halfband Filter can be individually bypassed using an internal programmable length delay. All control and coefficient registers are loaded through the LF InterfaceTM. This device operates at 3.3 V (5 V tolerant I/O) and is available in 160-lead PQFP package.
FEATURES
u 83 MHz Data Rate for HDTV Applications u Supports Multiple Video Formats Bi-Directional Conversions: - 4:2:2:4 - 4:4:4:4 - R/G/B/Key - Y/U/V/Key u Multiplexed and Non-multiplexed I/O Data u User-Programmable: - 3 x 3 Colorspace Converter - LUT for Gamma Correction - I/O Bias Compensation - Bypass Capability u 13-bit Data Path, Colorspace Converter Coefficients and Key Channel Scaling Coefficients u 160-lead PQFP
LF3370 BLOCK DIAGRAM
A12-0 B12-0 C12-0 D12-0
INPUT DE-MULTIPLEXER SECTION
INPUT BIAS ADDERS
1K x 13-Bit 55-TAP HALF-BAND INTERPOLATION/ DECIMATION FILTERS LOOK-UP-TABLES
COLORSPACE CONVERTER/ KEY SCALER
OUTPUT BIAS ADDERS
OUTPUT MULTIPLEXER SECTION
W12-0
X12-0
Y12-0
Z12-0
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HBLANK
FIGURE 1.
DATAPASS
DEVICES INCORPORATED
RESET
SYNC INPUT LOOK-UP-TABLE* CHROMA HALF-BAND FILTER / INTERPOLATOR 3 X 3 MATRIX MULTIPLY / KEY SCALER OUTPUT LOOK-UP-TABLE* OE 13 20
LIMIT
13
13 13 13 13 13 35
13
13 WOUT12-0
ROUND
INPUT BIAS ADDER 1K x 13-bit LUT*
SELECT
AIN12-0
1K x 13-bit LUT*
OUTPUT BIAS ADDER
13
LIMIT LIMIT
13
13
13 20 13 13
20
13
13
13 XOUT12-0
ROUND
SELECT
ROUND
INPUT BIAS ADDER 1K x 13-bit LUT* 1K x 13-bit LUT*
SELECT
BIN12-0
HALF-BAND FILTER/ INTERPOLATOR
OUTPUT BIAS ADDER
INPUT COLORSPACE CONVERTER
13
LIMIT LIMIT
OUTPUT MUX
DEMUX
13 3
13
13 20
20
13
13
13
13
13
ROUND
ROUND
INPUT BIAS ADDER 1K x 13-bit LUT*
SELECT SELECT
13
CF12-0
LD
LF INTERFACE
PAUSE
CLK
2 2
2 CA1-0
SELECT
3
ROUND
LIMIT
LF3370 FUNCTIONAL BLOCK DIAGRAM (HALF-BAND FILTER TO COLORSPACE ARRANGEMENT)
2
COEFFICIENT BANKS 0-9 KEY SCALER
13 2 35 13 13 20 RSL1-0
CIN12-0
HALF-BAND FILTER/ INTERPOLATOR
1K x 13-bit LUT*
OUTPUT BIAS ADDER
YOUT12-0
13
13
13 2
13 1
13 2
13 ZOUT12-0
DIN12-0
3-5
1
2 OUTBIAS1-0 HF0
INBIAS1-0
CONFIGURATION AND CONTROL REGISTERS
FLAG GENERATOR
HF1
* UP TO ONE LOOK-UP-TABLE MAY BE USED PER DATA PATH. THE INHERENT DELAY THROUGH THE LOOK-UP-TABLE IS TWO REGARDLESS OF WHETHER IT IS USED OR NOT.
High-Definition Video Format Converter
Video Imaging Products
LF3370
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NOTE: NUMBERS IN REGISTERS INDICATE NUMBER OF PIPELINE DELAYS WHICH IS ALSO EQUIVALENT TO NUMBER OF PIPELINE DELAYS THROUGH THAT PARTICULAR FUNCTIONAL BLOCK
HBLANK
FIGURE 2.
DATAPASS
DEVICES INCORPORATED
RESET
SYNC INPUT LOOK-UP-TABLE* CHROMA HALF-BAND FILTER / INTERPOLATOR 3 X 3 MATRIX MULTIPLY / KEY SCALER OUTPUT LOOK-UP-TABLE* OE 13 20
LIMIT
13
13 13 13 35 13 13 13
13 WOUT12-0
ROUND
INPUT BIAS ADDER 1K x 13-bit LUT*
SELECT
AIN12-0
1K x 13-bit LUT*
OUTPUT BIAS ADDER
13 20
LIMIT LIMIT
13
13
13 20 13 13
13
13
13 XOUT12-0
ROUND
SELECT
ROUND
INPUT BIAS ADDER 1K x 13-bit LUT* 1K x 13-bit LUT*
SELECT
BIN12-0
HALF-BAND FILTER/ DECIMATOR
OUTPUT BIAS ADDER
INPUT COLORSPACE CONVERTER
13 20
LIMIT LIMIT
OUTPUT MUX
DEMUX
13 3
13
13 20 13
13
13
13
13
ROUND
SELECT
ROUND
INPUT BIAS ADDER 1K x 13-bit LUT*
SELECT
13
CF12-0
LD
LF INTERFACE
PAUSE
CLK CA1-0
2 2
SELECT
3
ROUND
LIMIT
LF3370 FUNCTIONAL BLOCK DIAGRAM (COLORSPACE TO HALF-BAND FILTER ARRANGEMENT)
3
COEFFICIENT BANKS 0-9 KEY SCALER
13 2 13 20 13 35 2 RSL1-0
CIN12-0
HALF-BAND FILTER/ DECIMATOR
1K x 13-bit LUT*
OUTPUT BIAS ADDER
YOUT12-0
13
13
13 2
13 1
13 2
13 ZOUT12-0
DIN12-0
3-5
1
2 OUTBIAS1-0 HF0
INBIAS1-0
CONFIGURATION AND CONTROL REGISTERS
FLAG GENERATOR
HF1
* UP TO ONE LOOK-UP-TABLE MAY BE USED PER DATA PATH. THE INHERENT DELAY THROUGH THE LOOK-UP-TABLE IS TWO REGARDLESS OF WHETHER IT IS USED OR NOT.
High-Definition Video Format Converter
Video Imaging Products
LF3370
03/13/2001-LDS.3370-F
NOTE: NUMBERS IN REGISTERS INDICATE NUMBER OF PIPELINE DELAYS WHICH IS ALSO EQUIVALENT TO NUMBER OF PIPELINE DELAYS THROUGH THAT PARTICULAR FUNCTIONAL BLOCK
LF3370
DEVICES INCORPORATED
High-Definition Video Format Converter
HF1/HF0 -- HBlank Flags HF1 and HF0 are two general purpose flags used to indicate when a 20-bit counter reaches its user-defined terminal count; a HIGH to LOW transition of HBLANK and/or RESET will reset the flags. Controls LD -- Configuration Load When LD is LOW, data on CF12-0 is latched into the LF3370 LF InterfaceTM on the rising edge of CLK. When LD is HIGH, data is not loaded into the LF Interface TM. When enabling the LF Interface TM for data input, a latched HIGH to LOW transition of LD is required in order for the input circuitry to function properly. Therefore, LD must be set HIGH immediately after power up to ensure proper operation of the input circuitry. SYNC -- Synchronization for data alignment SYNC control signal is required to properly synchronize the input demultiplexer, output multiplexer, and halfband filters to the data flowing through the LF3370. A latched HIGH to LOW transition tells the core which sample corresponds to a Cb/Cr sample for proper de-multiplexing and multiplexing. This signal will also synchronize the half-band filters into a decimation/interpolation sequence. This signal is latched on the rising edge of CLK. DATAPASS -- Datapass Mode DATAPASS is used to place the LF3370 in a mode of operation that allows the user to pass data through the core (Input/Output Bias Adders, LUTs, Hafband Interpolator/ Decimator, Colorspace/Key Scaler) without any processing. This signal is latched on the rising edge of CLK. INBIAS1-0 -- Input Bias Control INBIAS1-0 determines which of the four user-programmable Input Bias registers are used to sum with the input data. These pins are latched on the rising edge of CLK. OUTBIAS1-0 -- Output Bias Control OUTBIAS1-0 determines which of the four user-programmable Output Bias registers are used to sum with the output data.These pins are latched on the rising edge of CLK. RSL1-0 -- Round/Select/Limit Control RSL1-0 determines which of the userprogrammable Round/Select/Limit registers (RSL registers) are used in the RSL circuitry. A value of 00 on RSL1-0 selects RSL register 0. A value of 01 selects RSL register 1 and so on. RSL1-0 is latched on the rising edge of CLK. OE -- Output Enable When OE is LOW, W12-0, X12-0, Y12-0, and Z12-0 are enabled for output. When OE is HIGH, W12-0, X12-0, Y12-0, and Z12-0 are placed in a highimpedance state. PAUSE -- LF InterfaceTM Pause When PAUSE is HIGH, the LF3370 LF InterfaceTM loading sequence is halted until PAUSE is returned to a LOW state. This effectively allows the user to load coefficients and control registers at a slower rate than the master clock. This pin is latched HBLANK -- Horizontal Blanking Control HBLANK is used for data replacement corresponding to user-selectable blanking levels. A HIGH to LOW transition resets the counter and the HFx flags.This signal is latched on the rising edge of CLK.
SIGNAL DEFINITIONS Power VCC and GND +3.3 V power supply. All power pins must be connected. Clock CLK -- Master Clock The rising edge of CLK strobes all enabled registers. To guarantee data integrity, a minimum of 25KHz must be maintained. Inputs A12-0, B12-0, C12-0, D12-0 -- Data Inputs A12-0, B12-0, C12-0, and D12-0 are the 13-bit registered data input ports. Data is latched on the rising edge of CLK. CF12-0 -- Coefficient Input CF12-0 is used to address and load Colorspace/Key Scaler coefficient banks, Round/Select/Limit registers, and Configuration registers. Data present on CF12-0 is latched into the LF InterfaceTM on the rising edge of CLK when LD is LOW. CA1-0 -- Coefficient Address CA1-0 determines which of the four user-programmable Colorspace/Key Scaler Coefficients are used. Outputs W12-0 , X12-0 , Y12-0 , Z12-0 -- Data Outputs W12-0, X12-0, Y12-0, and Z12-0 are the 13-bit registered data output ports. Outputs are updated on the rising edge of CLK.
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LF3370
DEVICES INCORPORATED
High-Definition Video Format Converter
TABLE 1.
Input Channel A12-0 B12-0 C12-0 D12-0 Output Channel W12-0 X12-0 Y12-0 Z12-0
on the rising edge of CLK. RESET -- Reset RESET is used to reset all programmable flags and line up clock edges during single muxed input or single muxed output events. RESET is used at power up or just after device configuration. This pin is latched on the rising edge of CLK. LF3370DeviceInitialization This section explains how to initialize the device for proper operation. It also serves as a summary of all conditions that should be considered before using the device or for troubleshooting. Configuration Register 0 and Configuration Register 1 must be loaded before operation of the device. If Core Bypassing is desired, Configuration Register 2 must be loaded before use. If use of the Half-Band Filters is desired, at least one Half-Band Filter RSL Register Set must be loaded and selected for each Half-Band Filter. If use of the Matrix Multiplier/Key Scaler is desired, at least one Matrix Multiplier/Key Scaler RSL Register Set and coefficient address must be loaded and selected for each channel. If use of the Input Bias Adder is desired, at least one Input Bias Adder Register must be loaded and selected before use. If use of the Output Bias Adder is desired, at least one Output Bias Adder Register must be loaded and selected before use. If use of the Look-Up Table is desired, the Look-Up Table must be loaded before use. When using a single channel input or output with interleaved video, SYNC and RESET should be used for proper initialization as shown in Figure 5. If 12 bits or less input data is desired, the input data should be shifted so the MSBs are aligned. Input Demultiplexer The input demultiplexer section acts as a buffer between the user's datapath and the
INPUT/OUTPUT FORMATS
4:4:4:4 R G B Key 4:4:4:4 R G B Key Input Format* 4:2:2:4 4:2:2:4 Y Cb Y Cb/Cr 4:2:2:4 Y/Cb/Cr N/A N/A Key 4:2:2:4 Y/Cb/Cr N/A N/A Key
Cr N/A Key Key Output Format* 4:2:2:4 4:2:2:4 Y Cb Cr Key Y Cb/Cr N/A Key
* Not all input/output combinations are valid. If single channel interleaved video is used on either the input or output, the core clock will be running at CLK/2. Thus the maximum input, output, and core data rate must be considered.
FIGURE 3. INPUT AND OUTPUT FORMATS
INPUT BIAS ADDER/OUTPUT BIAS ADDER Input Data 12 11 10 -212 211 210
(Sign)
Output Data 12 11 10 -212 211 210
(Sign)
210 22 21 20
210 22 21 20
MATRIX MULTIPLIER/KEY SCALER Input Data 12 11 10 -212 211 210
(Sign)
Coefficient Data 12 11 10 -20 2-1 2-2
(Sign)
210 22 21 20
210 2-10 2-11 2-12
*Matrix Multiplier Output F19 F18 F17 -215 214 213
(Sign)
*Key Scaler Output F19 F18 F17 -213 212 211
(Sign)
F2 F1 F0 2-2 2-3 2-4
F2 F1 F0 2-4 2-5 2-6
*Format of Matrix Multiplier/Key Scaler ouput feeding the RSL Circuitry. F19-F0 corresponds to 20 MSBs of which a 13-bit window can be selected from F19-F4 .
HALF-BAND FILTER Input Data 12 11 10 -212 211 210
(Sign)
210 22 21 20 **Filter Output (Interpolate) F19 F18 F17 -213 212 211
(Sign)
**Filter Output (Non-Interpolate) F19 F18 F17 -212 211 210
(Sign)
F2 F1 F0 2-5 2-6 2-7
F2 F1 F0 2-4 2-5 2-6
*Format of Half-Band Filter ouput feeding the RSL Circuitry. F19-F0 corresponds to 20 MSBs of which a 13-bit window can be selected from F19-F4 (see Table 3).
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LF3370
DEVICES INCORPORATED
High-Definition Video Format Converter
simply passed through the input demultiplexer with a latency that matches the other three channels. If video data is non-interleaved and presented to input ports A12-0, B12-0, and C12-0, no demultiplexing is performed. The three channels are passed unmodified into the LF3370 core with a delay of 3 CLK cycles. For this operation, bits 0 and 1 must both be set to 1 in Configuration Register 0 (see Table 5). If video data is on two channels (see Figure 4), one channel of non-interleaved video and one channel of interleaved video, it is assumed that non-interleaved video is presented to input port A12-0 (i.e., Luma)
LF3370's core. Data may be presented on input ports A12-0, B12-0, and C12-0 as three channels of non-interleaved input data, one channel non-interleaved and one channel interleaved input data, or one channel of interleaved data (see Table 1 for various video input schemes). D12-0 is the Key channel input port; the Key channel is
FIGURE 4. INPUT PROCESSING 4:2:2:4 (INTERLEAVED CHROMA ON CHANNEL B)
1 CLK RESET SYNC A12-0 B12-0 D12-0 A'12-0** B'12-0** C'12-0** D'12-0** * Demultiplexed Input Data (Output of Demux Section) K'0 Y0 CB0 K0 Y1 CR0 K1 Y2 CB2 K2 Y3 CR2 K3 Y'0 CB'0 CR'0 K'1 K'2 Y4 CB4 K4 Y'1 Y5 CR4 K5 Y'2 CB'2 CR'2 K'3 K'4 Y6 CB6 K6 Y'3 Y7 CR6 K7 Y'4 CB'4 CR'4 K'5 K'6 Y8 CB8 K8 Y'5 Y9 CR8 K9 Y'6 Y10 CB10 K10 Y'7 CB'6 CR'6 K'7 Y11 CR10 K11 Y'8 CB'6 CR'6 K'8 Y12 CB12 K12 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FIGURE 5. INPUT PROCESSING 4:2:2:4 (INTERLEAVED LUMA/CHROMA ON CHANNEL A)
1 CLK RESET CLK/2* SYNC A12-0 D12-0 A'12-0** B'12-0** C'12-0** D'12-0** K'0 CB0 K0 Y0 CR0 K1 Y1 CB2 K2 Y'0 CB'0 CR'0 K'1 K'2 Y2 CR2 K3 Y'1 Y3 CB4 K4 Y'2 CB'1 CR'1 K'3 Y4 CR4 K5 Y'3 Y5 CB6 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
* Core Clock (Internally Generated and Synchronized to CLK by RESET) Used Only When Single Channel Interleaved Input or Output Video is Used. ** Demultiplexed Input Data (Output of Demux Section)
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LF3370
DEVICES INCORPORATED
High-Definition Video Format Converter
tant that unused input ports be set either HIGH or LOW. Output Multiplexer The output multiplexer section can be configured in various ways to accommodate the video system. Bits 2 and 3 of Configuration Register 0 determines the number of output channels that the LF3370 will drive. Z12-0 is the Key channel output port; the Key channel simply gets passed through the output multiplexer with a latency that matches the other three channels. If three separate output channels of noninterleaved video are desired, no multiplexing is performed. The three channels are passed through the output multiplexer unmodified on the output ports W12-0, X12-0, and Y12-0 with a delay of 2 CLK cycles. For this operation, bits 2 and 3 must both be set to 1 in Configuration Register 0 (see Table 5). If one channel of non-interleaved video (i.e., Luma) and one channel of interleaved video (i.e., Chroma) is desired (see Figure 6), non-interleaved video will be driven to the output port W12-0 and interleaved video will be driven to the output port X12-0 with a delay of 2 CLK cycles. For this operation, bit 2 must be set to 0 and bit 3 must be set to 1 in Configuration Register 0 (see Table 5). If 4:2:2 interleaved video on one port is desired (see Figure 7), interleaved video will be driven to the output port W12-0 with a delay of 4 CLK cycles. For this operation, bit 2 must be set to 1 and bit 3 must be set to 0 in Configuration Register 0 (see Table 5). All output multiplexing operations are initiated by the latched HIGH to LOW transitions of SYNC which synchronizes the multiplexed output data to the LF3370 core (see SYNC discussion). SYNC SYNC control signal is required to properly synchronize the input demultiplexer, output multiplexer, and
and interleaved video is presented to input port B12-0 (i.e., Chroma). The input demultiplexer, in this case, separates video data on B12-0 and outputs two channels of separated video into the LF3370 core with a delay of 4 CLK cycles. For this operation, bit 0 must be set to 0 and bit 1 must be set to 1 in Configuration Register 0 (see Table 5). If 4:2:2 video data is on one channel interleaved (see Figure 5), it is assumed that interleaved video is presented to input port A12-0. The input demultiplexer, in this case, separates video data on A12-0 and outputs three channels of separated video into the LF3370 core with a delay of 5 CLK cycles. In this case, the core will run at half of the CLK rate and valid data will be output at at half of the CLK rate. For this operation, bit 0 must be set to 1 and bit 1 must be set to 0 in Configuration Register 0 (see Table 5). All input demultiplexing operations are controlled by the latched HIGH to LOW transitions of SYNC which synchronizes the LF3370 core to the multiplexed input data (see SYNC discussion). It is impor-
FIGURE 6. OUTPUTTING 4:2:2:4 (INTERLEAVED CHROMA ON CHANNEL X)
CLK W12-0 X12-0 Y0 (Output SYNC)* Z12-0 K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 Y0 CB0 Y1 CR0 Y2 CB2 Y3 CR2 Y4 CB4 Y5 CR4 Y6 CB6 Y7 CR6 Y8 CB8 Y9 CR8 Y10 CB10 Y11 CR10 Y12 CB12 Y13 CR12 Y14 CB14 Y15 CR14 Y16 CB16 Y17 CR16
* There will be a HIGH to LOW transition on every Cb sample
FIGURE 7. OUTPUTTING 4:2:2:4 (INTERLEAVED LUMA/CHROMA ON CHANNEL W)
CLK W12-0 Y0 (Output SYNC)* Z12-0 K0 K1 K2 K3 K4 K5 K6 K7 K8 CB0 Y0 CR0 Y1 CB2 Y2 CR2 Y3 CB4 Y4 CR4 Y5 CB6 Y6 CR6 Y7 CR8 Y8
* There will be a HIGH to LOW transition on every Cb sample
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LF3370
DEVICES INCORPORATED
High-Definition Video Format Converter
synchronization is desired. Therefore, when there is a HIGH to LOW transition on SYNC, the following is assumed: Cb will occur on the first LOW on SYNC that is latched, Cb will occur every two clock cycles if interleaved Chroma is presented to the input port B12-0, Cb will occur every 4 clock cycles if single channel 4:2:2 interleaved video is presented to the input port A12-0. SYNC control signal is also used to synchronize the interpolation/decimation output data from the Half-Band Filter to the Output Multiplexer. This synchronization is done automatically. RESET
13
halfband filters to the data flowing through the LF3370. A latched HIGH to LOW transition on SYNC control signal is needed to initialize the device to mark the beginning of valid data. In addition, if 4:2:2 interleaved video data is desired for input or output, a HIGH to LOW transition on SYNC must be registered by a simultaneous rising edge of CLK and CLK/2. CLK/2 is an internal clock that must be synchronized to CLK by use of RESET only if the core is running at half the rate of CLK (see RESET discussio n and Figures 4 & 5). Furthermore, SYNC is used to identify one interleaved data set from another. For example, in the case of interleaved Chroma, Cb and Cr samples must be properly demultiplexed and synchronized for processing. To differentiate a Cb sample from Cr, there needs to be a HIGH to LOW transition on SYNC on the first Cb sample (see Figure 4 & 5); SYNC can also be toggled on every Cb sample for re-synchronization. In the case that Cb is the first valid data word, SYNC may be used only once in device initialization and kept low until re-
FIGURE 8. INPUT BIAS
R3 2 INBIAS1-0 R0
13 13 From Input Demux 13 13
FIGURE 9. OUTPUT BIAS
R3 2 OUTBIAS1-0 R0
RESET should be used when initializing the device for proper operation. It is used to synchronize the LF3370 core clock to the master clock. In the case that single channel 4:2:2 interleaved video data is desired either on the input or output, thus using only one input or one output port (not including Key data), the internal clock rate will be half (CLK/2) of the master clock rate (CLK). In this case, RESET is needed to synchronize the rising edge of CLK/2 to a known rising edge of CLK (see Figure 4). For example, after configuring the LF3370 and before
13 From Core
13
streaming valid data through the part, a RESET event should be used to align the clock edges (see Figure 4 & 5). Furthermore, RESET will clear HF0 and HF1. A LOW state detected on RESET on a rising edge of clock will clear flags HF0 and HF1 on the following rising edge of clock. Please note HBLANK should be
FIGURE 10.
CLK HBLANK 20-bit COUNTER HF0 HF1 A'12-0* B'12-0* C'12-0* D'12-0*
HBLANK AND COUNTER
1 2 3 4 5 6 7 8 9 10 11 12 13 14
15 16 17 18
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
DN DN DN DN
HBLANK Word A
DN+3 DN+3 DN+3 DN+3
DN+4 DN+4 DN+4 DN+4
DN+5 DN+5 DN+5 DN+5
DN+6 DN+6 DN+6 DN+6
DN+7 DN+7 DN+7 DN+7
DN+8 DN+8 DN+8 DN+8
DN+9 DN+9 DN+9 DN+9
DN+10 DN+10 DN+10 DN+10
DN+11 DN+11 DN+11 DN+11
HBLANK Word A
HBLANK Word B
HBLANK Word B
HBLANK Word C
HBLANK Word C
HBLANK Word D
HBLANK Word D
* Data values at output of Input LUT section In this example, HF0 Count Value is set to 3 and HF1 Count Value is set to 5
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DEVICES INCORPORATED
High-Definition Video Format Converter
are injected on the next rising clock edge when HBLANK is LOW. In addition, HBLANK clears flags HF0 and HF1 and resets a 20-bit incrementing counter (0 1,048,575). If a HIGH to LOW transition on HBLANK is detected on a rising edge of clock, HF0 and HF1 are cleared and the counter is reset on the following rising edge of clock (see Figure 10). Key Channel blanking may be independently enabled or disabled using Congifuration Register 1 (see Table 6). HF0/HF1 and Counter HF0 and HF1 are two independent flags that are set when the pre-programmed HF0 or HF1 count value is equal to the 20bit incrementing counter value. For each flag, one user-defined 20-bit count value can be programmed. When HF0 or HF1 count value is equal to the counter value, HF0 or HF1 is set on the next rising edge of clock. Once the flags are set, they must be reset if they are needed again. The counter will increment by one at the rate of CLK and can be reset by HBLANK. The counter will continue to loop if not
used to clear HF0 and HF1 during normal operation (see HBLANK discussion). HBLANK HBLANK is used to replace portions of the input data with user-defined blanking levels. When HBLANK is LOW, blanking level words are injected into the data stream immediately after the Input LUT section regardless of this section being used or not. While HBLANK is LOW, blanking level words are continually injected into the datapath with userdefined blanking words. Blanking words
FIGURE 11.
13 13
MATRIX MULTIPLIER AND KEY SCALER
26 26
13 Coef Bank 0
13
13
26
26
28
20(MSB) RSL
13
A'
13 Coef Bank 1
13
13
26
26
13 Coef Bank 2 13 13 26 26
13 Coef Bank 3
13
13
26
26
28
20(MSB) RSL
13
B'
13 Coef Bank 4
13
13
26
26
13 Coef Bank 5 13 13 26 26
A
13 13 13 26 26 28 20(MSB) RSL 13 13 13 26 26 13
B
Coef Bank 6
C'
C
Coef Bank 7 13 Coef Bank 8
13
13
26
26
20(MSB) RSL
13
D
13 Coef Bank 9
D'
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High-Definition Video Format Converter
programmed and selected by CA1-0. A value of 00 on CA1-0 selects Coefficient Set 0 on each of the 9 coefficient banks. A value of 01 selects Coefficient Set 1 and so on. CA1-0 may be changed every clock cycle if desired. Coefficient bank loading is discussed in the LF InterfaceTM. The total pipeline latency from the input of the Matrix Multiplier to the output of the RSL Circuitry is 6 CLK cycles and new output data is subsequently available every clock cycle thereafter. If matrix multiplication is not desired, using the appropriate combination of coefficient values while keeping in mind bit weighting, an identity matrix may be set up to bypass the Matrix Multiplier section (see also First Operation Select in the Bypass Options discussion). Key Scaler The Key channel is equiped with a 13 x 13bit Key Scaler (see Figure 11) producing a truncated 20-bit output which is then fed into the RSL circuitry (see Figure 13). Up to four user-defined 13-bit coefficients can be programmed and selected by CA1-0. Input/Output formats are shown in Figure 3. The total pipeline latency from the input of the Key Scaler to the output of the RSL Circuitry is 6 CLK cycles and new output data is subsequently available every clock cycle thereafter. If scaling is not desired, load and select a Key Scaler Coefficient value of 1 (see also First Operation Select in the Bypass Options duscussion). Half-Band Filter There are two internal Half-Band filters in the LF3370. These Half-Band filters can either interpolate, decimate, or pass through data found on channel B and channel C. Data on channel A and channel D in this section pass through a programmable 127 x 13-bit delay (see Bypass Section). The filter section (as show in Figure 12) is a fixed-coefficient, linear-phase half-band (low-pass) interpolating/decimating digital filter. The filter in this section is a 55-tap transversal FIR with 13-bit coefficients as shown in Table 3. The frequency response (Figure 14) is in full compliance with SMPTE 260M. This section can be configured for 2:1 interpolation, 1:2 decimation, or pass-through mode by setting bits 5-8 in Configuration Register 0 (see Table 5). This section can also be placed before or after the matrix multi-
reset. HF0 and HF1 count value register loading is discussed in the LF InterfaceTM. Please note, using HBLANK is the recommended way of clearing HF0 and HF1 flags but they can be cleared by RESET, normally performed during device initialization. RESET will not reset the counter. Input/Output Bias Adder The programmable Input/Output Bias Adders can be used to subtract or add a 13-bit offset to the data. Input and output data formats for the two sections are shown in Figure 3. By using INBIAS1-0, the user may select one of four programmed Input Bias Adder values (see Figure 8). By using OUTBIAS1-0, the user may select one of four programmed Output Bias Adder values (see Figure 9). A value of 00 on INBIAS1-0/OUTBIAS1-0 selects Input/Output Bias Adder Register 0. A value of 01 selects Input/Output Bias Adder Register 1 and so on. INBIAS1-0/OUTBIAS1-0 may be changed every clock cycle if desired. If a bias is not desired, then bits 11 & 12 of Configuration Register 1 can be set up to independently disable the input and output bias values. Thus, effectively zeroing the function. The total pipeline latency from the input to the output for each of the two sections is one CLK cycle. Input/Output Bias Adder Register loading is discussed in the LF InterfaceTM section. 3 x 3 Matrix Multiplier Processing almost 550 million colors, three simultaneous 13-bit input and output channels are utilized to implement a 3 x 3matrix multiplication (triple dot product). Each truncated 20-bit output is the sum of all three input words multiplied by the appropriate coefficients (see Figure 11). These outputs are then fed into the RSL circuitry (see Figure 13). Input/Output formats are shown in Figure 3. For each of the nine multipliers, up to four user-defined 13-bit coefficients can be
FIGURE 12. 1:2 INTERPOLATION / 2:1 DECIMATION HALF-BAND FILTERS
VARIABLE LENGTH BYPASS DELAY 127 x 13-Bit 13
B'
13 INTERPOLATION CIRCUIT 55-TAP FIR FILTER DECIMATION CIRCUIT
B
RSL
CONFIGURATION / CONTROL REGISTERS
13
C
INTERPOLATION CIRCUIT
55-TAP FIR FILTER
DECIMATION CIRCUIT
RSL
13
C'
VARIABLE LENGTH BYPASS DELAY 127 x 13-Bit
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corresponding output peak is 35 clock cycles.
S3 S0 UL3 LL3 UL0 LL0
FIGURE 13. RSL CIRCUITRY
R3 2 RSL1-0 R0
20 20 From Core ROUND 20
13 13 SELECT
13 13 LIMIT 13
TABLE 2.
SLCT1-0 00 01 10 11
SELECT FORMATS
S12 S11 S10 S9 S8 S7 S6 S5 F9 S4 F8 F9 S3 F7 F8 F9 S2 F6 F7 F8 F9 S1 F5 F6 F7 F8 S0 F4 F5 F6 F7 F16 F15 F14 F13 F12 F17 F16 F15 F14 F13 F18 F17 F16 F15 F14 F19 F18 F17 F16 F15 F11 F10
F12 F11 F10
F13 F12 F11 F10
F14 F13 F12 F11 F10
plier by setting bit 4 in Configuration Register 0 (see Table 5). The maximum input and output clock rate this section can operate at is the CLK rate. The total internal pipeline latency from the input to the output of this section (including RSL circuitry) as shown in Figure 12 is 6 cycles. To perform interpolation, the input data rate of this section will be half of CLK rate. Please note the maximum output data
rate is the CLK rate. To perform decimation, the output data rate of this section will be half of the input data rate. One output sample is obtained for every two input samples. Once an impulse is clocked into the HalfBand Filter section, the 55-value output response begins after 8 clock cycles and ends after 62 clock cycles. The pipeline latency from the input of an impulse to its
The input/output formats are always in two's complement format as shown in Figure 3. In Interpolate Mode, the gain of the Half-Band Filter is halved (due to half of the input samples being padded with zeros). A right shifted Select window is required to maintain an overall filter gain of 1. It is possible that ringing on the filter's output could cause the high order bit (bit F18 in Figure 3 - Interpolate Filter Output Bit Weighting) to become HIGH. If a right shifted Select window is used, this F18 bit becomes the sign bit of the Selected window - and the output is erroneously considered negative. To ensure that no overflow conditions occur, an internal Limiter within each Half-Band Filter monitors its output. During Interpolate mode, this Limiter clamps the output word to 3FFFFH (20-bit maximum positive value ) 2) or C0000H (20-bit maximum negative value ) 2) if a positive or negative overflow occurs respectively. The internal 24-bits of the Half-Band Filter are truncated to 20bits and then passed to the Round section of the RSL circuitry; see RSL section for further details. This section is fully bypassable by use of programmable delays (see Bypass Options section for further details). Look-Up Table Three optional programmable Input/ Output 1K x 13-bit LUTs have been provided for Channels A, B, and C for various uses such as Gamma Correction. There are NOT actually two LUTs per channel as shown in Figures 1 and 2; only one LUT per channel can be selected for use at any given time. The latency through a LUT section is 2 cycles. This latency is present on the datapath regardless of whether the LUT is in use or not. When using a LUT, the appropriate addressed value will be passed as an
FIGURE 14.
0 -10 -20
FREQUENCY RESPONSE OF FILTER
GAIN (dB)
-30 -40 -50 -60 -70 -80 0 0.1S 0.2S 0.3S 0.4S 0.5S
FREQUENCY (NORMALIZED)
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Registers are used in each Select Circuitry (see Table 2). A value of 00 on RSL1-0 selects Select Register 0. A value of 01 selects Select Register 1 and so on. RSL1-0 may be changed every clock cycle if desired. This allows the 13-bit window to be changed every clock cycle. Select Register loading is discussed in the LF InterfaceTM section. Limiting The Limiting Circuitry found in the Matrix Multiplier and Half-Band Filter sections work in the same manner. The Limit Registers determine the valid range of output values for each of these two sections. There are four 13-bit Limit Registers for each section. RSL1-0 determines which of the four Limit Registers are used in each Limiting Circuitry (see Figure 13). A value of 00 on RSL1-0 selects Limit Register 0. A value of 01 selects Limit Register 1 and so on. Each Limit Register contains an upper and lower limit value. If the value fed to the Limiting Circuitry is less than the lower limit, the lower limit value is passed as the Matrix Multiplier section's or HalfBand filter section's output. If the value fed to the Limiting Circuitry is greater than the upper limit, the upper limit value is passed as the Matrix Multiplier section's or Half-Band filter section's output. RSL1-0 may be changed every clock cycle if desired thus allowing the limit range to be changed every clock cycle. When loading limit values into the device, the upper limit must be greater than the lower limit. The most negative and most positive values you can load into the Limit Registers are 0FFFH and 1000H. Limit Register loading is discussed in the LF InterfaceTM section. LF InterfaceTM The LF InterfaceTM is used to load the Configuration Registers, Matrix Multiplier/Key Scaler Coefficient Banks, LookUp Tables, Input/Output Bias registers, RSL registers, HF0 and HF1 Count Values, and Horizontal Blanking Levels.
output of the LUT section. The Gamma LUT address can be chosen from any of the 4 possible10-bit words that are `window' selected from the13-bit Input data bus. Configuring the desired LUT address selector position is accomplished by programming bits 10 & 9 of Configuration Register 1. Once the LUT Select Data position is programmed, it is meant to control all three Gamma LUTs. Therefore, the address selector positions of the three LUTs cannot be independently controlled. LUT loading is discussed in the LF InterfaceTM section. Rounding The rounding circuitry found in the Matrix Multiplier and Half-Band Filter sections work in the same manner. The truncated 20 MSBs from the Matrix Multiplier or Half-Band Filter output may be rounded by being added to the contents of one of the four Round Registers (see Figure 13). Each round register is 20 bits wide and userprogrammable. This allows the Matrix Multiplier's or Half-Band Filter's output to be rounded to any precision required. RSL1-0 determines which of the four Round Registers are used in each Rounding Circuitry. A value of 00 on RSL1-0 selects Round Register 0. A value of 01 selects Round Register 1 and so on. RSL10 may be changed every clock cycle if desired. If rounding is not desired, the user must load and select a Round Register with value of 0. Round Register loading is discussed in the LF InterfaceTM section. Selecting The selecting circuitry found in the Matrix Multiplier and Half-Band Filter sections work in the same manner. The output word of the Matrix Multiplier and HalfBand Filter feeding the RSL circuitry is the 20 MSBs. However, only 13 bits may be sent to the next section. Therefore, the Select Register determines which 13-bits are passed. There are four select registers; RSL1-0 determines which of the four Select
TABLE 3.
TAP 1, 55 2, 54 3, 53 4, 52 5, 51 6, 50 7, 49 8, 48 9, 47 10, 46 11, 45 12, 44 13, 43 14, 42 15, 41 16, 40 17, 39 18, 38 19, 37 20, 36 21, 35 22, 34 23, 33 24, 32 25, 31 26, 30 27, 29 28 (center)
HALF-BAND FILTER IMPULSE RESPONSE
Impulse Response Out (Non-Interpolated Bit Weighing) 20-bit (MSB) Filter Out (HEX) Decimal Equivalent FFE35 0 002D2 0 FFB5C 0 00725 0 FF508 0 00F95 0 FEA10 0 01E59 0 FD6A8 0 0393E 0 FAF1B 0 0798D 0 F2BD2 0 28B30 401BC -0.0008755 0 0.0013771 0 -0.00226593 0 0.0034885 0 -0.0053558 0 0.0076084 0 -0.01071167 0 0.0148182 0 -0.02018738 0 0.0279503 0 -0.0394993 0 0.05935097 0 -0.10360334 0 0.3179626 0.500846862
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FIGURE 15. BYPASS BLOCK DIAGRAM
13
VARIABLE LENGTH BYPASS DELAY (127 x 13-Bit ) VARIABLE LENGTH BYPASS DELAY (127 x 13-Bit )
13
13
13
A, B, C, D
INPUT DEMUX SECTION
INPUT BIAS SECTION
LUT SECTION
MATRIX MULTIPLIER and KEY SCALER SECTION
HALF-BAND FILTER SECTION
LUT SECTION
OUTPUT BIAS SECTION
OUTPUT MUX SECTION
W, X, Y, Z
In this example, the Matrix-Multipler/Key Scaler Section feeds the Half-Band Filter Section. This arrangement is reversible.
FIGURE 16.
CLK
CORE BYPASS
W1 W2
DATAPASS Core Data Bypass Data Output* D0 B0 D1 B1 D2 B2 D0 D3 B3 D1 D4 B4 D2 D5 B5 D3 D6 B6 D4 D7 B7 D5 D8 B8 B6 D9 B9 B7 D10 B10 B8 D11 B11 B9 D12 B12 B10 D13 B13 B11 D14 B14 B12 D15 B15 D13 D16 B16 D14 D17 B17 D15
* In this example, the Output Multiplexer is in a mode where the delay through the section is 2 CLK cycles. Only one channel is shown in this example, however, the other three channels behave in the same manner. The example assumes that the bypass RAM length is set to the length of the core data path. W1: Bypass data is output to the output port and replaces core data. W2: Core data is output to the output port and replaces bypass data.
TABLE 4. CONFIGURATION/CONTROL REGISTERS ADDRESSING SUMMARY
DESCRIPTION Coefficient Registers Configuration Registers Look-Up Table - Channel `A' Look-Up Table - Channel `B' Look-Up Table - Channel `C' Input Bias Registers - Channel `A' Input Bias Registers - Channel `B' Input Bias Registers - Channel `C' Output Bias Registers - Channel `A' Output Bias Registers - Channel `B' Output Bias Registers - Channel `C' HF0 Count Value HF1 Count Value Matrix Mult. RSL Registers - Channel `A' Matrix Mult. RSL Registers - Channel `B' Matrix Mult. RSL Registers - Channel `C' Key Scaler RSL Registers Half-Band Filter RSL Registers - Channel `B' Half-Band Filter RSL Registers - Channel `C' ADDRESS RANGE (HEX) 0000 - 0003 0200 - 020A 0300 0400 0500 0600 - 0603 0700 - 0703 0800 - 0803 0900 - 0903 0A00 - 0A03 0B00 - 0B03 0C00 0D00 0E00 - 0E03 0F00 - 0F03 1000 - 1003 1100 - 1103 1200 - 1203 1300 - 1303
LD is used to enable and disable the LF InterfaceTM. When LD goes LOW, the LF InterfaceTM is enabled for data input. The first value fed into the interface on CF12-0 is an address which determines what the interface is going to load (see Table 4). For example, to load address Bias Adder Register 2 of the channel B Output Bias Adder, the first data value into the LF InterfaceTM should be 0A02H. To load RSL Register 1 for the Keyscaler RSL, the first data value should be 1101H. The first address value should be loaded into the interface on the same clock cycle that latches the HIGH to LOW transition of LD. The next value(s) loaded into the interface are the data value(s) which will be stored in the bank or register defined by the address value. When loading coefficient banks, the interface will expect ten values to be loaded into the device after the address value. The ten values are coefficients 0 through 8 and the Keyscale coefficient. When loading Configuration or Bias Registers, the interface will expect one value after the address value. When loading RSL registers, the interface will
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TABLE 5. CONFIGURATION REGISTER 0 - ADDRESS 200H
BITS 1-0 FUNCTION Video Input Format DESCRIPTION 00 : 01 : 10 : 11 : 00 : 01 : 10 : 11 : 0: 1: 00 : 01 : 10 : 11 : 00 : 01 : 10 : 11 : 0: 1: Reserved Single Channel Interleaved Video Dual Channel Interleaved Video 3 Channel Non-Interleaved Video Reserved Single Channel Interleaved Video Dual Channel Interleaved Video 3 Channel Non-Interleaved Video Filter Feeds Matrix Multiplier Matrix Multiplier Feeds Filter Pass Through Filter Interpolate Decimate Bypass Filter Pass Through Filter Interpolate Decimate Bypass Filter Normal Order of Operations Select First Operation Only
expect four values after the address value. When loading gamma look-up tables, the interface will expect 1024 values after the address value. When loading HBLANK flag counts, the interface will expect 2 values after the address value. The coefficient banks, configuration registers, RSL registers, etc., are not loaded with data until all data values for the specified address are loaded into the LF Interface. In other words, the coefficient banks are not written until all ten coefficients have been loaded into the LF InterfaceTM. A RSL register is not written to until all four data words are loaded. After the last data value is loaded, the interface will expect a new address value on the next clock cycle. After the next address value is loaded, data loading will begin again as previously discussed. PAUSE allows the user to effectively slow the rate of data loading through the LF InterfaceTM. When PAUSE is HIGH, the LF InterfaceTM held until PAUSE is is returned LOW. Figure 19 shows the effects of PAUSE while loading Matrix Multiplier/Key Scaler coefficients. Table 28 shows an example of loading a bias value into the Input Bias Adder Register. In this example, a bias value of 007FH is loaded into the Channel `C' Input Bias Adder Register 1 (0B01H). Table 29 shows an example of loading a bias value into the Output Bias Adder Register. In this example, a bias value of 0010H is loaded into Channel `A' Output Bias Adder Register 3 (0903H). Table 30 shows an example of loading data into the Matrix Multiplier/Key Scaler Coefficient Banks. In this example, the following values are loaded into Coefficient Register Set 2 (0002H): 0000H, 0001H, 0002H, 0003H, 0004H, 0005H, 0006H, 0007H, 0008H, and 0009H. Table 31 shows an example of loading the HF0 Flag Count Value. In this example, a 20-bit HF0 Flag Count Value of B3C27H is loaded into the HF0 Flag Count Value
3-2
Video Output Format
4 6-5
Functional Arrangement Half-Band Filter Control Channel `B'
8-7
Half-Band Filter Control Channel `C'
9 12-10
First Operation Select Reserved
Must be Set to Zero
TABLE 6. CONFIGURATION REGISTER 1 - ADDRESS 201H
BITS 1-0 FUNCTION Look-Up Table Control Channel `A' DESCRIPTION 00 : 01 : 10 : 11 : 00 : 01 : 10 : 11 : 00 : 01 : 10 : 11 : 0: Disable Look-Up Table Enable Look-Up Table on Enable Look-Up Table on Reserved Disable Look-Up Table Enable Look-Up Table on Enable Look-Up Table on Reserved Input Output
3-2
Look-Up Table Control Channel `B'
Input Output
5-4
Look-Up Table Control Channel `C'
6
HBLANK Control `Key' Channel
Disable Look-Up Table Enable Look-Up Table on Input Enable Look-Up Table on Output Reserved Disable Horizontal Blanking Option During HBLANK Period 1 : Enable Horizontal Blanking Option During HBLANK Period Output Channel `A' to W12-0 Output Channel `B' to W12-0 Output Channel `C' to W12-0 Output Channel `D' to W12-0 Select Address Data [9:0] Select Address Data [10:1] Select Address Data [11:2] Select Address Data [12:3]
8-7
Data Bypass Mode `W' Output Channel Mux Control
10-9
Look-Up Table Input Address Selection Control
00 : 01 : 10 : 11 : 00 : 01 : 10 : 11 :
11 12
Input Bias Disable Output Bias Disable
0 : Enable Input Bias 1 : Disable Input Bias 0 : Enable Output Bias 1 : Disable Output Bias
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Scaler Section, and Output Bias and feeds the Output Multiplexer. Loading Configuration Register 2 programs the length of all four Core Bypass Delays (see Table 7). A LOW state detected on DATAPASS on a rising edge of clock will output bypassed data to the output port on the following rising edge of CLK (see Figure X). In addition, any of the four bypassed channels can be passed to the `W' output channel during a `bypass' event. For this operation, use bits 7 and 8 of Configuration Register 1 (see Table 6). Half-Band Filter Bypass At all times, while data is being fed into the Half-Band Filter section, channels A, B, C, and Key are fed into programmable length delays. When the Half-Band Filter(s) are set to filter bypass mode, that particular channel passes through a programmable delay and is not filtered. Since there are only two Half-Band Filters in this section found on channels B and C, channels A and Key are always passed through their respective programmable delays. Please note, when using a single channel video input or video output (interleaved 4:2:2), the Core Bypass Delay must be
Register (0C00H). The HF1 Flag Count Value is loaded in the same manner using the appropriate address. Table 32 shows an example of loading Round/Select/Limit values. In this example, Channel `A' Matrix Multiplier Register Set 0 (0E00H) is loaded with a 20bit Round value of 00020H, a 2-bit Select value of 10H, a 13-bit Upper Limit value of 0FFFH, and a 13-bit Lower Limit value of 1001H. Other RSL registers are loaded in the same manner using the appropriate address. Table 33 shows an example of loading a Configuration Register. In this example, Configuration Register 0 (0200H) is loaded with 00AEH. This will setup the Input Section to handle Luma on input port A12-0 and interleaved Chroma on the input port B12-0. The Output Section is setup to output RGB on the output ports W12-0, X12-0, Y12-0. The `functional arrangement' is setup in such a way that the Half-Band Filter section is placed before the Matrix Multiplier section. The Half-Band Filters are setup for 1:2 interpolation and `normal order of operations' is selected. BYPASS OPTIONS
TABLE 7.
BITS 6-0 12-7
CONFIGURATION REGISTER 2 - ADDRESS 202H
FUNCTION Core Bypass Delay Length Reserved DESCRIPTION Length of Core Bypass Delay Minus 2 Must be Set to Zero
TABLE 8.
BITS 6-0 12-7
CONFIGURATION REGISTER 3 - ADDRESS 203H
FUNCTION Channel `A' Filter Section Bypass Delay Length Reserved DESCRIPTION Length of Filter Bypass Delay Minus 2 Must be Set to Zero
TABLE 9.
Core Bypass At all times during the normal operation of the LF3370, video data on channels A, B, C, and D are simultaneously being fed from the output of the Input Demultiplexer into the programmable Core Bypass Delay (see Figure 15). This allows users to switch between processed video and unprocessed (bypassed) data on-the-fly. There is a separate Core Bypass Delay for each channel. Each Core Bypass Delay can be programmed for a length of 2 up to 129 CLK cycles for delay matching between the bypass path and the core as well as other operations. The Core Bypass Delay bypasses the Input Bias, Input LUT, Half-Band Filter, Matrix Multiplier/Key
BITS 6-0 12-7
CONFIGURATION REGISTER 4 - ADDRESS 204H
FUNCTION Channel `B' Filter Section Bypass Delay Length Reserved DESCRIPTION Length of Filter Bypass Delay Minus 2 Must be Set to Zero
TABLE 10. CONFIGURATION REGISTER 5 - ADDRESS 205H
BITS 6-0 12-7 FUNCTION Channel `C' Filter Section Bypass Delay Length Reserved DESCRIPTION Length of Filter Bypass Delay Minus 2 Must be Set to Zero
TABLE 11. CONFIGURATION REGISTER 6 - ADDRESS 206H
BITS 6-0 12-7 FUNCTION Key Channel Filter Section Bypass Delay Length Reserved DESCRIPTION Length of Filter Bypass Delay Minus 2 Must be Set to Zero
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programmed to double the length [(desired length x 2) - 2)] to properly align data due to the core running at half the CLK rate. First Operation Select `First Operation Select' is a bypassing option where you select to use the first functional block (Half-Band Filter or Matrix Multiplier/Key Scaler) in any given arrangement. If the device was arranged in such a way that the Half-Band Filter section fed the Matrix Multiplier/Key Scaler section and `First Operation Select' was enabled, the Half-Band Filter section will be used and the Matrix Multiplier/Key Scaler section will be bypassed. If the device was arranged in such a way that the Matrix Multiplier/Key Scaler section fed the Half-Band Filter section and `First Operation Select' was enabled, the Matrix Multiplier/Key Scaler section will be used - its output will be routed directly to the output LUT section. Unlike in other bypassing options , the total pipeline latency of the LF3370 is reduced by the appropriate delay. If the Half-Band Filter section was bypassed by this method, the overall pipeline latency should be reduced by 35 CLK cycles. If the Matrix Multiplier section was bypassed by this method, the overall pipeline latency should be reduced by 6 CLK cycles. This function is implemented by configuring bit 9 of Configuration Register 0. The `Functional Arrangement' of the device is determined by configuring bit 4 of Configuration Register 0.
TABLE 12.
BITS 12-0
CONFIGURATION REGISTER 12 - ADDRESS 207
DESCRIPTION Channel `A' Blanking Level Word
FUNCTION Channel `A' Blanking Word
TABLE 13.
BITS 12-0
CONFIGURATION REGISTER 13- ADDRESS 208
DESCRIPTION Channel `B' Blanking Level Word
FUNCTION Channel `B' Blanking Word
TABLE 14.
BITS 12-0
CONFIGURATION REGISTER 14 - ADDRESS 209
DESCRIPTION Channel `C' Blanking Level Word
FUNCTION Channel `C' Blanking Word
TABLE 15. CONFIGURATION REGISTER 15 - ADDRESS 20A
BITS 12-0 FUNCTION Channel `D' Blanking Word DESCRIPTION Channel `D' Blanking Level Word
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TABLE 17. CHANNEL `B' INPUT BIAS REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 0700 0701 0702 0703
TABLE 16. CHANNEL `A' INPUT BIAS REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 0600 0601 0602 0603
TABLE 18. CHANNEL `C' INPUT BIAS REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 0800 0801 0802 0803
TABLE 19. CHANNEL `A' OUTPUT BIAS REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 0900 0901 0902 0903
TABLE 20. CHANNEL `B' OUTPUT BIAS REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 0A00 0A01 0A02 0A03
TABLE 21. CHANNEL `C' OUTPUT BIAS REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 0B00 0B01 0B02 0B03
TABLE 22. CHANNEL `A' MATRIX MULT. RSL REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 0E00 0E01 0E02 0E03
TABLE 23. CHANNEL `B' MATRIX MULT. RSL REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 0F00 0F01 0F02 0F03
TABLE 24. CHANNEL `C' MATRIX MULT. RSL REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 1000 1001 1002 1003
TABLE 25. `KEY' CHANNEL MATRIX MULT. RSL REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 1100 1101 1102 1103
TABLE 26. CHANNEL `B' HALFBAND FILTER RSL REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 1200 1201 1202 1203
TABLE 27. CHANNEL `C' HALFBAND FILTER RSL REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 1300 1301 1302 1303
TABLE 28 HFX COUNT VALUE REGISTERS
COUNT 0 1 ADDRESS (HEX) 0C00 0D00
TABLE 29. HORIZONTAL BLANKING LEVEL ADDRESS
CHANNEL `A' `B' `C' `D' ADDRESS (HEX) 0207 0208 0209 020A
TABLE 30. MATRIX MULT. & SCALER COEFFICIENT REGISTERS
REGISTER 0 1 2 3 ADDRESS (HEX) 0000 0001 0002 0003
TABLE 31.LOOK-UP TABLE ADDRESSING
CHANNEL `A' `B' `C' ADDRESS (HEX) 0300 0400 0500
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TABLE 32. INTPUT BIAS ADDER REGISTER LOADING FORMAT
CF12 Address Word 0 0 0 CF11 1 0 CF10 0 0 CF9 1 0 CF8 1 0 CF7 0 0 CF6 0 1 CF5 0 1 CF4 0 1 CF3 0 1 CF2 0 1 CF1 0 1 CF0 1 1
TABLE 33. OUTPUT BIAS ADDER REGISTER LOADING FORMAT
CF12 Address Word 0 0 0 CF11 1 0 CF10 0 0 CF9 0 0 CF8 1 0 CF7 0 0 CF6 0 0 CF5 0 0 CF4 0 1 CF3 0 0 CF2 0 0 CF1 1 0 CF0 1 0
TABLE 34
Address Coef Bank 0 Coef Bank 1 Coef Bank 2 Coef Bank 3 Coef Bank 4 Coef Bank 5 Coef Bank 6 Coef Bank 7 Coef Bank 8 Coef Bank 9
MATRIX MULTIPLIER/KEY SCALER COEFFICIENT BANK LOADING FORMAT
CF12 0 0 0 0 0 0 0 0 0 0 0 CF11 0 0 0 0 0 0 0 0 0 0 0 CF10 0 0 0 0 0 0 0 0 0 0 0 CF9 0 0 0 0 0 0 0 0 0 0 0 CF8 0 0 0 0 0 0 0 0 0 0 0 CF7 0 0 0 0 0 0 0 0 0 0 0 CF6 0 0 0 0 0 0 0 0 0 0 0 CF5 0 0 0 0 0 0 0 0 0 0 0 CF4 0 0 0 0 0 0 0 0 0 0 0 CF3 0 0 0 0 0 0 0 0 0 1 1 CF2 0 0 0 0 0 1 1 1 1 0 0 CF1 1 0 0 1 1 0 0 1 1 0 0 CF0 0 0 1 0 1 0 1 0 1 0 1
TABLE 35.
Address Word 0 Word 1
HFX COUNT VALUE LOADING FORMAT
CF12 0 R R CF11 1 1 R CF10 1 1 R CF9 0 0 R CF8 0 0 R
HF19
CF7 0 0 1
CF6 0 0 0
CF5 0 1 1
CF4 0 0 1
CF3 0 0 0
CF2 0 1 0
CF1 0 1 1
CF0 0 1 1
HF0
TABLE 36. RSL REGISTER LOADING FORMAT
CF12 Address Word 0 Word 1 Word 2 Word 3
UL12 LL12
CF11 1 0 R 1 0
CF10 1 0 R 1 0
S1
CF9 1 0 0 1 0
CF8 0 0 1 1 0
S0 R19
CF7 0 0 0 1 0
CF6 0 0 0 1 0
CF5 0 1 0 1 0
CF4 0 0 0 1 0
CF3 0 0 0 1 0
CF2 0 0 0 1 0
CF1 0 0 0 1 0
CF0 0 0 0 1 1
UL0 LL0 R0
0 R R 0 1
TABLE 37.
Address Word 0
CONFIGURATION REGISTER LOADING FORMAT
CF12 0 0 CF11 0 0 CF10 0 0 CF9 1 0 CF8 0 0 CF7 0 1 CF6 0 0 CF5 0 1 CF4 0 0 CF3 0 1 CF2 0 1 CF1 0 1 CF0 0 0
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DEVICES INCORPORATED
High-Definition Video Format Converter
FIGURE 17.CONFIGURATION, INPUT/OUTPUT BIAS ADDER, RSL, AND HBLANK LEVEL REGISTER LOADING SEQUENCE
CONFIG REG IN/OUT BIAS REG RSL REGISTER HBLANK LEVEL REGISTER
CLK W1 LD W2 W3 W4
CF12-0
ADDR1
DATA1
ADDR2
DATA1
ADDR3
DATA1
DATA2
DATA3
DATA4
ADDR4
DATA1
DATA2
W1: Configuration Register updated and effective on this rising clock edge. W2: Input or Output Bias Adder Register updated and effective on this rising clock edge. W3: RSL Register Set updated and effective on this rising clock edge. W4: Horizontal Blanking Level Register updated and effective on this rising clock edge.
FIGURE 18.LOOK-UP TABLE LOADING SEQUENCE
CLK W1 LD
CF11-0
ADDR1
N0
N1
N2
N3
N4
N1019
N1020
N1021
N1022
N1023
W1: LUT updated and effective on this rising clock edge.
FIGURE 19.MATRIX MULTIPLIER/KEY SCALER COEFFICIENT BANK LOADING SEQUENCE
CLK W1 LD
CF12-0
ADDR1
COEF0
COEF1
COEF2
COEF3
COEF4
COEF5
COEF6
ADDR7
COEF8
COEF9
W1: Matrix Multiplier/Key Scaler Coefficient Set updated and effective on this active rising clock edge.
FIGURE 20.MATRIX MULTIPLIER/KEY SCALER COEFFICIENT BANK LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
CLK W1 PAUSE LD
CF12-0
ADDR1
COEF0
COEF1
COEF9
W1: Matrix Multiplier/Key Scaler Coefficient Set updated and effective on this active rising clock edge.
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DEVICES INCORPORATED
High-Definition Video Format Converter
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 8)
Storage temperature ............................................................................................................. -65C to +150C Operating ambient temperature ................................................................................................... 0C to +70C VCC supply voltage with respect to ground ............................................................................ -0.5 V to +4.5 V Input signal with respect to ground ........................................................................................... -0.5 V to 5.5 V Signal applied to high impedance output .................................................................................. -0.5 V to 5.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ................................................................................................................................ > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode Active Operation, Commercial Temperature Range (Ambient) 0C to +70C Supply Voltage 3.00 V VCC 3.60 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol VOH VOL VIH VIL IIX IOZ ICC1 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic Input Capacitance Output Capacitance Ground VIN 5.25 V (Note 12) Ground VOUT 5.25 V (Note 12)
At Max Operating Frequency
Test Condition VCC = Min., IOH = -4 mA VCC = Min., IOL = 8.0 mA
Min 2.4
Typ
Max
Unit V
0.4 2.0 0.0 5.5 0.8 10 10 100 10 10
V V V A A mA pF pF
TA = 25C, f = 1 MHz TA = 25C, f = 1 MHz
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DEVICES INCORPORATED
High-Definition Video Format Converter
SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0C to +70C) Notes 9, 10 (ns)
LF3370- 12
Symbol Parameter Min Max
tCYC tPWL tPWH tS tH tSCT tHCT tD tDIS tENA
Cycle Time Clock Pulse Width Low Clock Pulse Width High Input Setup Time Input Hold Time Setup Time Control Inputs Hold Time Control Inputs Output Delay Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11)
12 5 5 4 0 4 0 8 10 10
SWITCHING WAVEFORMS:
1 CLK tS A, B, C, D12-0 tH
DATA I/O
2 3 tPWL
A, B, C, DN+1
4
5
6
7
A, B, C, DN
tPWH tCYC
CA1-0 CONTROLS (Except OE) OE
CAN
CAN+1
tSCT
tHCT
tDIS W, X, Y, Z12-0
tENA
HIGH IMPEDANCE W, X, Y, ZN-1
tD
W, X, Y, ZN
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DEVICES INCORPORATED
High-Definition Video Format Converter
LF3370- 12
COMMERCIAL OPERATING RANGE (0C to +70C) Notes 9, 10 (ns)
Symbol
Parameter
Min
Max
tCFS tCFH tLS tLH tPS tPH
Configuration Input Setup Configuration Input Hold Load Setup Time Load Hold Time PAUSE Setup Time PAUSE Hold Time
5.5 0 4 0 4 0
SWITCHING WAVEFORMS:
1 CLK tLS LD PAUSE tCFS CF11 0 tCFH tPWH
LF INTERFACETM
2 tPWL tCYC tPS tPH 3 4 tLH 5 6
ADDRESS
CF0
CF1
CF2
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DEVICES INCORPORATED
High-Definition Video Format Converter
ORDERING INFORMATION
BIN5 BIN4 BIN3 BIN2 BIN1 BIN0 CIN12 CIN11 CIN10 CIN9 CIN8 CIN7 CIN6 CIN5 CIN4 CIN3 CIN2 CIN1 CIN0 GND DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 Vcc CLK GND Vcc GND CA1 CA0 GND BIN6 BIN7 BIN8 BIN9 BIN10 BIN11 BIN12 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 Vcc RSL1 RSL0 GND CF0 CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9 CF10 CF11 CF12 LD PAUSE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
160-pin
Top View
INBIAS1 INBIAS0 OUTBIAS1 OUTBIAS0 DATAPASS HBLANK RESET SYNC GND ZOUT0 ZOUT1 ZOUT2 ZOUT3 ZOUT4 Vcc GND ZOUT5 ZOUT6 ZOUT7 ZOUT8 ZOUT9 Vcc GND ZOUT10 ZOUT11 ZOUT12 YOUT0 YOUT1 Vcc GND YOUT2 YOUT3 YOUT4 YOUT5 YOUT6 Vcc YOUT7 YOUT8 YOUT9 YOUT10
Speed
0C to +70C -- COMMERCIAL SCREENING
12 ns LF3370QC12
GND HF0 HF1 WOUT12 WOUT11 WOUT10 WOUT9 Vcc WOUT8 WOUT7 WOUT6 WOUT5 WOUT4 GND WOUT3 WOUT2 WOUT1 WOUT0 XOUT12 XOUT11 Vcc GND XOUT10 XOUT9 XOUT8 XOUT7 XOUT6 XOUT5 Vcc GND XOUT4 XOUT3 XOUT2 XOUT1 XOUT0 Vcc GND YOUT12 YOUT11 OE
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Plastic Quad Flatpack (Q6)
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DEVICES INCORPORATED
High-Definition Video Format Converter
Contact factory for additional information.
DEVICES INCORPORATED
1320 Orleans Drive Sunnyvale, CA 94089 tel. 800.851.0767 408.542.5400 fax. 408.542.0080 www.logicdevices.com apps@logicdevices.com applications hotline 408.542.5446 (08:00 17:00 Pacific)
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